1. Field of the Invention
The present disclosure generally relates to semiconductor memory devices and, more particularly, to a system which efficiently processes erroneous bits generated in a flash memory device.
A claim of priority under 35 U.S.C. §119 is made to Korean Patent Application No. 2006-85865, filed Sep. 6, 2006, the entire contents of which are hereby incorporated by reference.
2. Description of the Related Art
Many memory devices may inadvertently store defective data due to various reasons. In order to rectify this situation, various technologies for error detection and correction are used to recover or restore defective data. Data may be defective for various reasons. For example, data could be corrupted due to a variety of factors while being stored in a memory, or due to perturbations of data transmission channels between a source and destination.
Various approaches have been proposed to detect and correct defective data stored in memory devices. To this end, some of the well-known data error detecting and correcting techniques are the Reed-Solomon (RS) codes, Hamming codes, Bose-Chaudhury-Hocquenghem (BCH) codes, cyclic redundancy codes (CRC), and so forth. Moreover, in most applications employing nonvolatile memory devices, data is stored in these memory devices along with data known as error correction codes (ECC) (hereinafter, referred to as ‘ECC data’). ECC data are provided to correct erroneous bits generated during a read operation in a flash memory device. However, the number of error bits that are correctable by ECC data is limited.
FIG. 1 is a block diagram of a general flash memory device, and FIG. 2 is a timing diagram showing a read operation in the flash memory device shown in FIG. 1. First, referring to FIG. 1, a general flash memory device includes a memory cell array that has pluralities of memory blocks. Specifically, FIG. 1 shows a single memory block, e.g., BLK0. The memory block BLK0 has strings (or NAND strings) 10, each being connected to columns or bit lines. Each string includes a string selection transistor SST, a ground selection transistor GST, and memory cells (or memory cell transistors). Furthermore, each string also includes memory cells MC0˜MCn−1 serially connected between the selection transistors SST and GST. Gates of the selection transistors SST and GST are each coupled to string and ground selection lines SSL and GSL corresponding thereto, while control gates of the memory cell transistors MC0˜MCn−1 are coupled to word lines WL0˜WLn−1 corresponding thereto. In addition, bit lines BL0˜BLm−1 are connected to page buffers PB corresponding thereto.
In the read operation, as illustrated in FIG. 2, a selected word line (e.g., WL0) is driven with a voltage of 0V, while deselected word lines (e.g., WL1˜WLn−1) are driven with a read voltage Vread. During this operation, the string and ground selection lines SSL and GSL are driven with the read voltage Vread and the page buffers PB supply sensing currents to their corresponding bit lines BL0˜BLm−1. Voltages of the bit lines BL0˜BLm−1 may be determined by conditions of the memory cells coupled to the selected word line. For example, if the memory cell coupled to the selected word line is an on-cell, the bit line voltage corresponding thereto falls down to a ground voltage. In contrast, if the memory cell coupled to the selected word line is an off-cell, the bit line voltage corresponding thereto rises up to a power source voltage. Furthermore, the bit line voltages are detected by the page buffers PB as cell data.
For convenience of description, a memory cell coupled to a deselected word line is referred to as a deselected memory cell and a memory cell coupled to a selected word line is referred to as a selected memory cell. As stated above, in order to read data from the selected memory cell, the word lines of the deselected memory cell are supplied with the read voltage Vread. In particular, the read voltage Vread is set to a voltage level that is enough to turn on a memory cell transistor being conditioned in an off-state. During the read operation, the read voltage Vread is applied to the control gates of the deselected memory cell transistors, while the ground voltage is applied to a substrate (or bulk) of the deselected memory cell transistors. Furthermore, a predetermined voltage is applied to drains of the deselected memory cell transistors. This bias condition is similar to that for programming a cell. Because of that, as shown in FIG. 3, electrons may be injected into a floating gate of the deselected memory cell transistor from the substrate during the read operation. That is, the deselected memory cell transistors in on-states (or erased states) are softly programmed under the bias condition of the read operation, which is referred to as ‘read disturbance’ in general. This ‘read disturbance’ may be problematic.
For example, the read disturbance may gradually increase threshold voltages of memory cells conditioned in on-states (or erased states). As shown by dashed lines of FIG. 4, threshold voltages of the on-state memory cells may increase with the repetition of the read operation. This phenomenon may make an on-state memory cell be erroneously detected as an off-cell. This erroneous state detection of the cell because of an increase in the threshold voltage due to the read disturbance may cause a read failure.
As mentioned above, bit errors generated from the read operation can be repaired by techniques such as error detection and correction without any other remedial procedure such as a process of block replacement. Referring to FIG. 5, the probability of read failure may gradually increase with a repetition of the read operation. That is, data corrected by an error detection/correction operation is highly probable to have another error during the next read operation. When the number of error bits in read data is larger than the permitted number of error bits, a reserved memory block, which is additionally provided to a flash memory device, may be substituted for a memory block including defective data by using a remedial process such as block replacement.
Thus, as described above, once the read data includes error bits under the permitted error bit number, the error bits are repaired by means of a given process of error detection and correction. However, even when the read data has been for errors, it is very probable that the error-corrected data may have another error after the read operation. Therefore, there is a need for a technique to improve the reliability of error-corrected data.